List of registers of Accel 34 Click driver.
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List of registers of Accel 34 Click driver.
◆ ACCEL34_REG_ACT_INACT_CTL
| #define ACCEL34_REG_ACT_INACT_CTL 0x37 |
◆ ACCEL34_REG_BCLK
| #define ACCEL34_REG_BCLK 0x5B |
◆ ACCEL34_REG_CLK_CTRL
| #define ACCEL34_REG_CLK_CTRL 0x25 |
◆ ACCEL34_REG_DEV_DELTA_F0_X
| #define ACCEL34_REG_DEV_DELTA_F0_X 0x0E |
◆ ACCEL34_REG_DEV_DELTA_F0_Y
| #define ACCEL34_REG_DEV_DELTA_F0_Y 0x0F |
◆ ACCEL34_REG_DEV_DELTA_F0_Z
| #define ACCEL34_REG_DEV_DELTA_F0_Z 0x10 |
◆ ACCEL34_REG_DEV_DELTA_Q_X
| #define ACCEL34_REG_DEV_DELTA_Q_X 0x0B |
◆ ACCEL34_REG_DEV_DELTA_Q_Y
| #define ACCEL34_REG_DEV_DELTA_Q_Y 0x0C |
◆ ACCEL34_REG_DEV_DELTA_Q_Z
| #define ACCEL34_REG_DEV_DELTA_Q_Z 0x0D |
◆ ACCEL34_REG_DEVID_AD
| #define ACCEL34_REG_DEVID_AD 0x00 |
Accel 34 register map.
Specified register map of Accel 34 Click driver.
◆ ACCEL34_REG_DEVID_MST
| #define ACCEL34_REG_DEVID_MST 0x01 |
◆ ACCEL34_REG_DIG_EN
| #define ACCEL34_REG_DIG_EN 0x27 |
◆ ACCEL34_REG_FIFO_CFG0
| #define ACCEL34_REG_FIFO_CFG0 0x30 |
◆ ACCEL34_REG_FIFO_CFG1
| #define ACCEL34_REG_FIFO_CFG1 0x31 |
◆ ACCEL34_REG_FIFO_DATA
| #define ACCEL34_REG_FIFO_DATA 0x1D |
◆ ACCEL34_REG_FIFO_STATUS0
| #define ACCEL34_REG_FIFO_STATUS0 0x1E |
◆ ACCEL34_REG_FIFO_STATUS1
| #define ACCEL34_REG_FIFO_STATUS1 0x1F |
◆ ACCEL34_REG_FILTER
| #define ACCEL34_REG_FILTER 0x50 |
◆ ACCEL34_REG_FSYNC
| #define ACCEL34_REG_FSYNC 0x5C |
◆ ACCEL34_REG_INT0
| #define ACCEL34_REG_INT0 0x5D |
◆ ACCEL34_REG_INT0_MAP0
| #define ACCEL34_REG_INT0_MAP0 0x2B |
◆ ACCEL34_REG_INT0_MAP1
| #define ACCEL34_REG_INT0_MAP1 0x2C |
◆ ACCEL34_REG_INT1
| #define ACCEL34_REG_INT1 0x5E |
◆ ACCEL34_REG_INT1_MAP0
| #define ACCEL34_REG_INT1_MAP0 0x2D |
◆ ACCEL34_REG_INT1_MAP1
| #define ACCEL34_REG_INT1_MAP1 0x2E |
◆ ACCEL34_REG_MCLK
| #define ACCEL34_REG_MCLK 0x5A |
◆ ACCEL34_REG_MISC0
| #define ACCEL34_REG_MISC0 0x20 |
◆ ACCEL34_REG_MISC1
| #define ACCEL34_REG_MISC1 0x21 |
◆ ACCEL34_REG_MISO
| #define ACCEL34_REG_MISO 0x58 |
◆ ACCEL34_REG_NVM_CTL
| #define ACCEL34_REG_NVM_CTL 0x29 |
◆ ACCEL34_REG_OP_MODE
| #define ACCEL34_REG_OP_MODE 0x26 |
◆ ACCEL34_REG_OR_CFG
| #define ACCEL34_REG_OR_CFG 0x48 |
◆ ACCEL34_REG_PART_ID
| #define ACCEL34_REG_PART_ID 0x02 |
◆ ACCEL34_REG_PART_ID_REV_ID
| #define ACCEL34_REG_PART_ID_REV_ID 0x03 |
◆ ACCEL34_REG_PDM_CFG
| #define ACCEL34_REG_PDM_CFG 0x36 |
◆ ACCEL34_REG_RESET
| #define ACCEL34_REG_RESET 0x2A |
◆ ACCEL34_REG_SAR_I2C
| #define ACCEL34_REG_SAR_I2C 0x28 |
◆ ACCEL34_REG_SENS_DSM
| #define ACCEL34_REG_SENS_DSM 0x24 |
◆ ACCEL34_REG_SERIAL_NUMBER_0
| #define ACCEL34_REG_SERIAL_NUMBER_0 0x04 |
◆ ACCEL34_REG_SERIAL_NUMBER_1
| #define ACCEL34_REG_SERIAL_NUMBER_1 0x05 |
◆ ACCEL34_REG_SERIAL_NUMBER_2
| #define ACCEL34_REG_SERIAL_NUMBER_2 0x06 |
◆ ACCEL34_REG_SERIAL_NUMBER_3
| #define ACCEL34_REG_SERIAL_NUMBER_3 0x07 |
◆ ACCEL34_REG_SERIAL_NUMBER_4
| #define ACCEL34_REG_SERIAL_NUMBER_4 0x08 |
◆ ACCEL34_REG_SERIAL_NUMBER_5
| #define ACCEL34_REG_SERIAL_NUMBER_5 0x09 |
◆ ACCEL34_REG_SERIAL_NUMBER_6
| #define ACCEL34_REG_SERIAL_NUMBER_6 0x0A |
◆ ACCEL34_REG_SNSR_AXIS_EN
| #define ACCEL34_REG_SNSR_AXIS_EN 0x38 |
◆ ACCEL34_REG_SOUT0
| #define ACCEL34_REG_SOUT0 0x59 |
◆ ACCEL34_REG_SPT_CFG0
| #define ACCEL34_REG_SPT_CFG0 0x32 |
◆ ACCEL34_REG_SPT_CFG1
| #define ACCEL34_REG_SPT_CFG1 0x33 |
◆ ACCEL34_REG_SPT_CFG2
| #define ACCEL34_REG_SPT_CFG2 0x34 |
◆ ACCEL34_REG_STATUS0
| #define ACCEL34_REG_STATUS0 0x11 |
◆ ACCEL34_REG_STATUS1
| #define ACCEL34_REG_STATUS1 0x12 |
◆ ACCEL34_REG_STATUS2
| #define ACCEL34_REG_STATUS2 0x13 |
◆ ACCEL34_REG_STATUS3
| #define ACCEL34_REG_STATUS3 0x14 |
◆ ACCEL34_REG_SYNC_CFG
| #define ACCEL34_REG_SYNC_CFG 0x35 |
◆ ACCEL34_REG_TAP_CFG
| #define ACCEL34_REG_TAP_CFG 0x47 |
◆ ACCEL34_REG_TAP_DUR
| #define ACCEL34_REG_TAP_DUR 0x44 |
◆ ACCEL34_REG_TAP_LATENT
| #define ACCEL34_REG_TAP_LATENT 0x45 |
◆ ACCEL34_REG_TAP_THRESH
| #define ACCEL34_REG_TAP_THRESH 0x43 |
◆ ACCEL34_REG_TAP_WINDOW
| #define ACCEL34_REG_TAP_WINDOW 0x46 |
◆ ACCEL34_REG_TDATA_H
| #define ACCEL34_REG_TDATA_H 0x1B |
◆ ACCEL34_REG_TDATA_L
| #define ACCEL34_REG_TDATA_L 0x1C |
◆ ACCEL34_REG_THRESH_ACT_H
| #define ACCEL34_REG_THRESH_ACT_H 0x39 |
◆ ACCEL34_REG_THRESH_ACT_L
| #define ACCEL34_REG_THRESH_ACT_L 0x3A |
◆ ACCEL34_REG_THRESH_INACT_H
| #define ACCEL34_REG_THRESH_INACT_H 0x3E |
◆ ACCEL34_REG_THRESH_INACT_L
| #define ACCEL34_REG_THRESH_INACT_L 0x3F |
◆ ACCEL34_REG_TIME_ACT_H
| #define ACCEL34_REG_TIME_ACT_H 0x3B |
◆ ACCEL34_REG_TIME_ACT_L
| #define ACCEL34_REG_TIME_ACT_L 0x3D |
◆ ACCEL34_REG_TIME_ACT_M
| #define ACCEL34_REG_TIME_ACT_M 0x3C |
◆ ACCEL34_REG_TIME_INACT_H
| #define ACCEL34_REG_TIME_INACT_H 0x40 |
◆ ACCEL34_REG_TIME_INACT_L
| #define ACCEL34_REG_TIME_INACT_L 0x42 |
◆ ACCEL34_REG_TIME_INACT_M
| #define ACCEL34_REG_TIME_INACT_M 0x41 |
◆ ACCEL34_REG_TRIG_CFG
| #define ACCEL34_REG_TRIG_CFG 0x49 |
◆ ACCEL34_REG_USER_TEMP_SENS_0
| #define ACCEL34_REG_USER_TEMP_SENS_0 0x55 |
◆ ACCEL34_REG_USER_TEMP_SENS_1
| #define ACCEL34_REG_USER_TEMP_SENS_1 0x56 |
◆ ACCEL34_REG_X_DSM_OFFSET
| #define ACCEL34_REG_X_DSM_OFFSET 0x4D |
◆ ACCEL34_REG_X_SAR_OFFSET
| #define ACCEL34_REG_X_SAR_OFFSET 0x4A |
◆ ACCEL34_REG_XDATA_H
| #define ACCEL34_REG_XDATA_H 0x15 |
◆ ACCEL34_REG_XDATA_L
| #define ACCEL34_REG_XDATA_L 0x16 |
◆ ACCEL34_REG_Y_DSM_OFFSET
| #define ACCEL34_REG_Y_DSM_OFFSET 0x4E |
◆ ACCEL34_REG_Y_SAR_OFFSET
| #define ACCEL34_REG_Y_SAR_OFFSET 0x4B |
◆ ACCEL34_REG_YDATA_H
| #define ACCEL34_REG_YDATA_H 0x17 |
◆ ACCEL34_REG_YDATA_L
| #define ACCEL34_REG_YDATA_L 0x18 |
◆ ACCEL34_REG_Z_DSM_OFFSET
| #define ACCEL34_REG_Z_DSM_OFFSET 0x4F |
◆ ACCEL34_REG_Z_SAR_OFFSET
| #define ACCEL34_REG_Z_SAR_OFFSET 0x4C |
◆ ACCEL34_REG_ZDATA_H
| #define ACCEL34_REG_ZDATA_H 0x19 |
◆ ACCEL34_REG_ZDATA_L
| #define ACCEL34_REG_ZDATA_L 0x1A |